A memory controller receives read and write memory requests and in response issues row activate, row precharge, column read, and column write commands to a memory device, such as a dynamic random access memory (DRAM). To maximize memory bandwidth, conventional memory controllers group requests that access the same memory bank, so that the latency incurred for the row precharge and activate operation to access the particular bank is amortized over several accesses. When memory accesses are less frequent, the latency incurred by each access may increase, and processing performance may suffer.
There is thus a need for addressing these and/or other issues associated with the prior art.